Speed pattern generator for elevator systems

ABSTRACT

A speed pattern generator for elevator control which provides a time dependent speed reference pattern, with control over maximum jerk directly incorporated into the pattern itself. The speed pattern is developed by starting with a step signal whose two magnitudes determine maximum jerk. The specific magnitude of the step signal which is selected, and time spent at each magnitude of the step signal is determined by acceleration and speed feedback circuits. The step or jerk signal is integrated to provide an acceleration signal, and the acceleration signal is integrated to provide a speed pattern signal which, regardless of how fast the elevator system responds thereto, positively limits the maximum jerk.

Winkler Nov. 27, 1973 SPEED PATTERN GENERATOR FOR ELEVATOR SYSTEMS 3,627,080 12/1971 Yuminaka et a1. 187/29 Primary Examiner Bemard A. Gilheany Assistant Examiner-W. E. Duncanson, Jr. Attorney-A. T. Stratton et al.

[5 7 ABSTRACT A speed pattern generator for elevator control which provides a time dependent-speed reference pattern, with control over maximum jerk directly incorporated into the pattern itself. The speed pattern is developed by starting with a step signal whose two magnitudes determine maximum jerk. The specific magnitude of the step signal which is selected, and time spent at each magnitude of the step signal is determined by acceleration and speed feedback circuits. The step or jerk signal is integrated to provide an acceleration signal, and the acceleration signal is integrated to provide a speed pattern signal which, regardless of how fast the elevator system responds thereto, positively limits the maximum jerk.

17 Claims, 23 Drawing Figures TIMING coRRIooR CALL CONTROt 20 i --{MOTOR||=- TIMING 3 30m LANDING r 62 CAR CALL y CONTROL SWHRHES HATCHWAY H736 55 TIMING; 3 V H3 TO DOOR 2 CAR FLOOR HA'LL 56 DOOR OPERATOR SELECTOR LANTERNS 2nd LANDIN OPERATOR 58 G i [54 OI PFR Pasta L k g 9 J LER GENERATOR 24 50 I J 48 DISTANCE 56 i PULSES' d lsi LANDING PULSE DETECTOR 0 i 64 1Q v-2s 32 Y DE TECTOR Pmmgnunvzmn Q 3774.729

suzsf an or 19 n I uo FLOOR CORRIDOR CALLS CAR CAN CONSIDER WHEN TRAVELLING IN A GIVEN DIRECTION FIG. I l

PATENTEDRHV 27 973 saw 1 HF SPEED 7 DEMAND\ LEVEL FIG. I5B

PAIENIEDunvav ms SHEET 15 0F TIME RAMP GENERATOR DISTANCE SLOW DOWN N A Du T TIME RAMP GENERATOR TIME T EA E K A Wm w R m .s s( E L J E FIG. l6

FIG. 20A I084 VOLTAGE (T) INPLIT To FILTER AMPLIFIER ouTPuT I VOLTAGE V2 0F FILTER v, AMPLIFIER I I086 (VSE) 0 I TIME VOLTAGE (H INPUT TO FILTER AMPLIFIER VOLTAGE OUTPUT OF 2 FILTER VI AMPLIFIER L A I054 O I (VSE) TIME SPSW TOVSP FIG. 20B 

1. A speed pattern generator for providing a jerk controlled, time dependent speed pattern signal, comprising: first means providing a step signal switchable between first and second magnitudes representative of maximum rate of change of acceleration, second means integrating said step signal to provide an acceleration signal, third means integrating said acceleration signal to provide a speed pattern signal, and fourth means for controlling the switching of said step signal in response to said acceleration signal and said speed pattern signal.
 2. The speed pattern generator of claim 1 wherein the fourth means switches the step signal to a predetermined one of its first and second magnitudes during predetermined transitions between constant speed and constant acceleration portions of the speed pattern signal, and switches back and forth between the first and second magnitudes during portions of the speed pattern which provide constant parameters.
 3. The speed pattern generator of claim 1 wherein the first and second magnitudes of the step signal provide first and second currents of opposite polarity.
 4. The speed pattern generator of claim 3 wherein the fourth means controls the switching of the step signal to average the first and second currents to zero during the portions of the speed pattern which represent constant parameters.
 5. The speed pattern generator of claim 1 wherein the fourth means includes acceleration and speed feedback loops connected to be responsive to the second and third means, respectively.
 6. The speed pattern generator of claim 5 including means interconnecting the acceleration and speed feedback loops, such that the signal in the acceleration feedback loop modifies the signal in the speed feedback loop.
 7. The speed pattern generator of claim 6 wherein the acceleration and speed feedback loops each include means providing reference signals, and comparator means which com-pares the feedback signal with a reference signal, and wherein the acceleration feedback signal modifies the speed feedback signal to reduce the time required for the speed feedback signal to reach the level of its reference signal.
 8. The speed pattern generator of claim 1 wherein the fourth means includes acceleration reference and speed reference signals, acceleration and speed comparator means for comparing said acceleration reference and speed reference signals with the acceleration and speed pattern signals, respectively, and means for switching the step signal in response to said acceleration and speed comparator means
 9. The speed pattern generator of claim 8 wherein the speed pattern is initiated by a change in the magnitude of the speed reference signal from a first to a second magnitude.
 10. The speed pattern generator of claim 9 wherein the speed pattern includes a slowdown phase, with the slowdown phase of the speed pattern being initiated by a change in tHe magnitude of the speed reference signal from its second to its first magnitude.
 11. The speed pattern generator of claim 8 wherein the speed pattern signal includes a zero speed phase, a jerk controlled first transition phase, and a constant acceleration phase, with the first transition phase being initiated by a change in the magnitude of the speed reference signal and terminated by the acceleration comparator means when the acceleration signal reaches the level of the acceleration referenc.
 12. The speed pattern generator of claim 8 wherein the speed pattern signal includes a constant acceleration phase, a jerk controlled second transition phase, and a constant speed phase, and including means modifying the speed pattern signal applied to the speed comparator means with the acceleration signal, to cause the modified speed signal to reach the level of the reference signal earlier than would the unmodified speed signal, to enable the second transition phase to interconnect the constant acceleration and constant speed phases without overshoot.
 13. The speed pattern generator of claim 8 wherein the speed pattern signal includes a constant speed phase, a jerk controlled third transition phase, and a constant deceleration phase, and wherein the comparator means includes a deceleration comparator, with the third transition phase being initiated by a change in the magnitude of the speed reference signal and terminated by the deceleration comparator when the acceleration signal reaches the level of the acceleration reference.
 14. The speed pattern generator of claim 8 wherein the speed pattern signal includes a constant deceleration phase, a jerk controlled fourth transition phase, and a zero speed phase, and including means modifying the speed pattern signal applied to the speed comparator means with the acceleration signal, to cause the modified speed signal to reach the level of the reference signal earlier than would the unmodified speed signal, to enable the fourth transition phase to smoothly interconnect the constant deceleration and zero speed phases.
 15. A speed pattern generator for providing a jerk controlled, time dependent speed pattern signal for elevator motor control which controls the travel of an elevator car relative to a structure, comprising: first means providing a step signal switchable between first and second magnitudes representing maximum jerk, second means integrating said step signal to pro-vide an acceleration signal, third means integrating said acceleration signal to provide a speed pattern signal, a speed feedback loop responsive to the speed pattern signal for providing a speed feedback signal, said speed feedback loop including speed reference means switchable between predetermined magnitudes, and speed comparator means connected to compare the speed feedback and speed reference signals and provide an output indicative of their relationship, an acceleration feedback loop responsive to the acceleration signal for providing an acceleration feedback signal, said acceleration feedback loop including acceleration reference means, and first acceleration comparator means connected to compare the acceleration feedback signal and acceleration reference signal and provide an output indicative of their relationship, logic means providing output signals responsive to the outputs of said speed and acceleration comparators, and switching means connected to said logic means and said first means, switching the step signal to a selected magnitude in response to the output signal of the logic means during transitions between constant speed and constant acceleration to limit jerk during such transitions, and switching the step signal between its magnitudes at a rate which exceeds the response time of the elevator car, to maintain predetermined constant parameters during portions of the speed pattern when such parameters are to be kept constant.
 16. The speed pattern generator of claim 15 including means modifying thE speed feedback signal with the acceleration feedback signal, to reduce the time required for the speed feedback signal to reach the selected magnitude of the speed reference, and provide a jerk limited transition from a constant acceleration phase of the speed pattern to a constant speed phase without overshoot.
 17. The speed pattern generator of claim 15 wherein the speed pattern signal includes acceleration and deceleration phases, the acceleration signal is of one polarity during the acceleration phase, and of the opposite polarity during the deceleration phase, and including second acceleration comparator means in the acceleration feedback loop connected to compare the deceleration signal with the acceleration reference signal and provide an output indicative of their relationship, and means connecting the output of said second acceleration comparator means to the logic means. 